The differences between the original board described in QEX and the current version are:

1) The ADC has been changed from an Analog Devices AD9244 to a
Linear Technology LTC1746. Both are 14-bit ADCs and the SFDR
specifications for the LT part are better than the AD part. The LT ADC
allows the use of pin-compatible 12 or 14-bit 25, 50, 65 or 80 MSPS
ADCs if needed in the future.

2) The USB interface has been changed from an Agere USS2X1A to a
Cypress CY7C68001. The Agere part is an UTMI transceiver with an 8-bit
interface. The Cypress part has a 16-bit interface and incorporates the
USB device serial interface engine (SIE) so minimal FPGA resources are
required for USB. Both 12 and 480 MBPS USB are supported.

3) The new PCB is 3.9" x 4.7" and fits a Hammond 1455N1201A extruded
aluminum enclosure. This enclosure has flat aluminum front and rear panels
that may be easily machined to accept the DCP-1 connectors. The board
has six holes for 4-40 screws that may be used to mount it on standoffs or
for standard Keystone right-angle brackets to ground the PCB to the front
and rear panels of the enclosure.

4) The new I/O connectors are a 5-pin header for power (+3.3V and +5V), a
8-pin header for SPI, a 2-pin header for TCXO output, an RJ-45 for ADC and
DAC I/O and a USB type A (host) receptacle for ADC input. Alternatively,
3-pin (ADC) and 5-pin (DAC) headers may be used for analog I/O. The
RS-232/RS-485 I/O remains on an RJ-45 receptacle and the USB I/O on a
USB type B (device) receptacle. The headers have 25-mil sqaure pins on
100-mil centers.

5) The new PCB allows for installation of a right-angle SMA or SMB
receptacle for ADC sample clock output or input from an external
frequency standard, an 8-pin right-angle mini-DIN for SPI and a 20-pin
dual-row header for connecting an emulator.

6) The new PCB includes space for LC filters for the DAC outputs and the
ADC input.

7) The new PCB allows for installation of a TI PCM3501 audio CODEC
and associated components and has space for a dual 1/8" phone jack for
balanced line-level audio I/O.

8) All FPGA clocks are derived from the ADC clock output which is
generated by a TCVCXO attached to the ADC clock input.